A flash analog to digital converter (ADC) has a highest conversion rate because of its fully parallel architecture. However, an N-bit flash ADC needs 2N−1 comparators, which consume large power and occupy large area. An interpolation ADC is an alternative approach to reduce the complexity of flash ADC and still maintain the high conversion rate. A number of amplifiers and a number of reference voltages required in the interpolation ADC is less than those required in the flash ADC. The interpolation ADC includes multiple amplifiers and a comparator block. Before the outputs of the multiple amplifiers are fed into the comparator block, an interpolation block is inserted. The interpolation block combines the outputs of multiple amplifiers and generates interpolated signals, which contains information of the amplifiers. After interpolation processing, the comparator block deals with more quantization levels.
Interpolation ADC is effective in digitization of high bandwidth signals. However, there are inherent drawbacks associated with the interpolation ADC. An offset associated with the amplifiers, and the gain mismatch among the amplifiers causes degradation in performance of the interpolation ADC. Although, an absolute gain of an amplifier of the multiple amplifiers is not critical, a mismatch in gain among the amplifiers should ideally be low. Designing the amplifiers to compensate for these drawbacks in not possible when the interpolation ADC is used for high speed operation.